a. (011101)$_2$ – (110011)$_2$ using 2’s complement

1. Minuend: A = (011101)$_2$
2. Subtrahend: B = (110011)$_2$
3. Find 2's complement of B:
   • 1's complement of B = (001100)$_2$
   • 2's complement of B = 1's complement of B + 1 = (001100)$_2$ + (000001)$_2$ = (001101)$_2$
4. Add A to 2's complement of B:
   • A + (2's complement of B)
   • (011101)$_2$
   • • (001101)$_2$

   • ---

   • (101010)$_2$
5. Analyze result:
   • No carry-out from the most significant bit.
   • The result is negative and in 2's complement form.
6. Find the magnitude of the result:
   • Take 2's complement of (101010)$_2$:
     • 1's complement = (010101)$_2$
     • Add 1 = (010101)$_2$ + (000001)$_2$ = (010110)$_2$
7. Final Answer: -(010110)$_2$

b. (89344)${10}$ – (98654)${10}$ using 9’s complement

1. Minuend: A = 89344
2. Subtrahend: B = 98654
3. Find 9's complement of B:
   • 9's complement of B = 99999 - 98654 = 01345
4. Add A to 9's complement of B:
   • A + (9's complement of B)
   • 89344
   • • 01345

   • ---

   • 90689
5. Analyze result:
   • No end-around carry (no carry out from the leftmost digit).
   • The result is negative and in 9's complement form.
6. Find the magnitude of the result:
   • Take 9's complement of 90689:
     • 9's complement = 99999 - 90689 = 09310
7. Final Answer: -9310

A race condition, specifically the "race-around" condition, in a level-triggered JK flip-flop occurs when both J and K inputs are high (J=K=1) and the clock pulse remains high for a duration longer than the propagation delay of the flip-flop. In this scenario, the output can toggle back and forth multiple times within a single clock pulse, leading to an unpredictable final state after the clock pulse ends.

This issue is primarily resolved by using a Master-Slave JK flip-flop or by designing an edge-triggered JK flip-flop.

Resolution using Master-Slave JK Flip-Flop:

1. Configuration: A Master-Slave JK flip-flop consists of two cascaded level-triggered JK flip-flops: a Master flip-flop and a Slave flip-flop. The clock input to the Slave is inverted relative to the Master.
2. Operation during Clock HIGH:
   • When the clock signal is high, the Master flip-flop is enabled, allowing it to respond to the J and K inputs. It captures the state based on these inputs.
   • During this period, the Slave flip-flop is disabled because its clock input (inverted clock) is low. It retains its previous state, and its outputs are stable.
3. Operation during Clock LOW (transition from HIGH to LOW):
   • As the clock transitions from high to low (falling edge), the Master flip-flop becomes disabled, effectively locking its captured state.
   • Simultaneously, the Slave flip-flop becomes enabled (as its inverted clock input goes high). The Slave then copies the stable state from the outputs of the now-locked Master flip-flop to its own outputs (Q and Q').
4. Operation during Clock LOW:
   • When the clock signal is low, the Master flip-flop remains disabled, isolating it from any changes at the J and K inputs.
   • The Slave flip-flop is enabled but is only responding to the stable outputs of the Master, which are locked.
5. Prevention of Race-Around: This two-stage, clock-phased operation ensures that:
   • The inputs J and K can only affect the Master when the clock is high.
   • The output of the entire flip-flop (Q and Q' of the Slave) can only change when the clock goes low, copying the state from the Master.
   • The Master is isolated from its inputs (J, K) while the Slave is updating its output, preventing any further changes or toggling within the same clock cycle.
   • Consequently, the overall flip-flop updates its state only once per full clock cycle, typically at the falling edge, eliminating the race-around condition.

State Diagram
A state diagram is a graphical representation used to visualize the behavior of a finite state machine (FSM) or sequential logic circuits.

• Components: Consists of nodes (circles) representing the distinct states of the system and directed edges (arrows) representing transitions between these states.
• Transitions: Each transition is typically labeled with the input condition that causes the state change and the output generated during or after the transition.
• Purpose: Illustrates how the system's current state, combined with specific inputs, determines the next state and the corresponding outputs. It is fundamental in the design and analysis of sequential circuits.

Encoder
An encoder is a combinational logic circuit that converts a set of N input lines into a binary code of M output lines, where 2^M ≥ N.

• Function: It is designed such that when only one of its input lines is active (typically high), it produces a unique M-bit binary code corresponding to that active input line.
• Application: Commonly used to convert decimal or octal inputs into binary coded decimal (BCD) or pure binary format, respectively.
• Types: A common variation is the priority encoder, which resolves ambiguities when multiple input lines are active by assigning a priority to each input and encoding only the highest-priority active input.

Parallel Adder
A parallel adder is a combinational logic circuit that performs the addition of two binary numbers simultaneously across all bit positions.

• Construction: It is typically constructed using multiple full adder circuits connected in parallel. For N-bit numbers, N full adders are used (or one half adder for the least significant bit, followed by N-1 full adders).
• Operation: Each full adder receives two input bits (A_i, B_i) and a carry-in (C_i) from the less significant bit stage, producing a sum bit (S_i) and a carry-out (C_i+1) for the next stage.
• Advantage: Offers faster addition compared to serial adders because all bits are processed concurrently, though carry propagation delay (ripple carry) can still limit overall speed.