csc116

Digital Logic

Hard Exam Preparation: 3 days
Question Papers (6)
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FM: 60 PM: 24

Digital Logic

2078 Boards

Section A

Answer any two questions.

1

Design the sequential circuit with respect to the following state diagram using J-K flip flops.

question image

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2

Implement F = Σ(0, 2, 3, 4, 7) using

Multiplexer
Decoder
PLA

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3

Difference between synchronous and asynchronous counter. Design mode-7 synchronous counter using T-flip flop. Show necessary truth tables and k-maps.

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Section B

Answer any eight questions.

4

Provide one example where shift right operation can be used. Explain parallel-in-parallel-out register.

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5

Carry out the following task

Preform 1’s complement subtraction 110101 – 100101
Represent decimal number 0.125 into its binary form

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6

Derive the Boolean expression for sum and carry of half adder. Draw its combinational circuit. Implement it using only NAND gates.

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7

Express the Boolean function F = x + yz as product of max-terms.

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8

Minimize the Boolean function Boolean function using K-map
F(A, B, C, D) = Σ(0, 1, 3, 5, 7, 8, 9, 11, 13, 15)

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9

What are the practical implementations of up counter? Explain Binary ripple counter.

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10

Design a combinational circuit with three inputs and one output. The output is 1 when the binary value of the inputs is an odd number.

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11

Differentiate between PLA and PAL. Explain 4-bit magnitude comparator

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12

Write short notes on (Any Two)

Negative Logic
CMOS
EBCDIC

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